The invention relates to a method for fabricating a capacitor configuration and in particular to a method for fabricating a capacitor configuration in which the integration of ferroelectric capacitors fabricated by a single-step patterning process is possible in a simple manner.
Modern memory devices use elementary memory cells for storing information. The memory cells have a capacitor device or the like as an elementary memory element. The desire for large scale integrated memory devices having a plurality of essentially identical memory cells makes it necessary to apply a capacitor configuration having a plurality of identical capacitor devices on a substrate, which, in particular, is a semiconductor substrate or the like. In this case, on the surface of the substrate which is used as a basis, the surface, if appropriate, is made such that it is correspondingly pre-patterned. In each case a sequence of specific layers or material layers is formed locally at predefined locations for providing a capacitor device. Consequently, at each of these predefined locations on the surface of the substrate, there is produced an individual separate capacitor device as an essentially layered structure and, overall, a corresponding sequence of a plurality of identical capacitor devices which then form the corresponding capacitor configuration of the memory device. This method for constructing the corresponding elementary memory elements in the form of capacitor devices is used in many memory modules, for example RAM (Random Access Memory) modules, in particular in FeRAM memory devices.
In principle, a number of different procedures are conceivable for the application of the individual layers. In so-called multi-step methods, the sequence of the individual material layers is applied to the surface of the substrate used as a basis in each case in a plurality of process steps. On account of the cell enlargements which are known in the case of multi-step methods and have a disadvantageous effect with regard to the highest possible integration density in the memory modules, a procedure has been adopted in which corresponding layer configurations are formed in a single-step method, in particular in the case of the so-called stacked cell principle, in which the layer configuration of the capacitor device is in each case formed directly above assigned circuit configurations formed within the substrate and is not offset laterally with respect thereto as in the case of the so-called offset cell principle.
After the formation of the layer structures, precisely in the single-step method, with regard to the further process stepsxe2x80x94for example required annealing steps, external contact-connection to further metallization layers to be applied and the likexe2x80x94known methods encounter problems in preventing damage to the layer structure as a whole or to the individual layers e.g. on account of reactive processes with the process atmospherexe2x80x94in particular with oxygenxe2x80x94or on account of interactions between the layers, precisely in the lateral region of the layer structure.
Thus, it can happen, for example, that the plug connections applied on the substrate surface are partially oxidized in the process atmosphere, thereby impairing or interrupting a desired electrical contact between a region in the substrate used as a basis and layers of the capacitor. Furthermore, leakage current sources caused by material reconfigurations and/or other reactive or oxidative processes may also be problematic.
It is accordingly an object of the invention to provide a method for fabricating a capacitor device on a substrate which overcomes the above-mentioned disadvantages of the heretofore-known methods of this general type and with which the sequence of layers of the capacitor device can be formed with a particularly high quality and/or yield in a particularly simple manner.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a capacitor configuration including at least one capacitor device, the method includes the steps of:
providing a substrate;
applying a sequence of layers on the substrate by using a 2D patterning process wherein the layers of the sequence of layers respectively are applied in an area-covering manner and subsequently patterned with an etching operation in a common process step;
forming the layers of the sequence of layers locally on a surface of the substrate at respective given locations such that a capacitor device is provided; and
filling free intermediate regions of the surface of the substrate with at least one electrically insulating intermediate layer up to a level of a topmost layer of the capacitor device.
The method according to the invention for fabricating a capacitor configuration having at least one capacitor device wherein intermediate regions of the surface of the substrate which remain free are filled with at least a first, at least essentially electrically insulating intermediate layer, in particular in each case at least up to the level of a topmost layer of the capacitor device. By virtue of this measure, at least the lateral areas and edges of the formed sequence of layers of the capacitor device are mechanically covered and thus protected against undesirable mechanical conversion processes, in particular with the process atmosphere during subsequent process steps. Furthermore, what is also achieved by the electrical insulation is that adjacent layer sequences of adjacent capacitor devices do not acquire electrical contact, which is undesired.
Consequently, it is a basic idea of the present invention that, after the formation of the sequence of layers of the capacitor device, at least the lateral regions or edge regions of the layer sequence of the capacitor device are covered by a corresponding intermediate layer applied in the intermediate regions between the capacitor devices and are thus protected against undesirable chemical conversion processes. Consequently, it is possible to prevent, in particular, the situation in which, for example in an oxygen-containing process atmosphere, the bottommost layer is oxidatively attacked from the lateral region and, as a consequence thereof, the contact between the underlying substrate or corresponding conductivity regions of the substrate and the subsequent layer of the capacitor device is interrupted.
In a preferred mode of the method according to the invention, it is provided that a contact layer is applied to and/or patterned onto the at least one intermediate layer at least in regions, in particular in order in each case to be at least electrically contact-connected to the topmost layer of the capacitor device at least in a central or edge-remote region thereof. In this way, it is possible to realize, in particular, an electrical contact-connection of the capacitor device in the form of the sequence of layers and a corresponding connection to the outside world. In this case, the regions on which the contact layer is applied on the first intermediate layer are chosen precisely in such a way as to produce a corresponding circuit configuration of the plurality of capacitor devices of the capacitor configuration.
During the patterning process of the sequence of layers of the capacitor devices, so-called redeposition effects often occur during specific processes. In this case, during material erosion operations, for example, portions of the eroded material are attached and deposited in the region of the surface of the substrate and, in particular, on the edge regions or lateral regions of the sequence of layers of the capacitor devices. These redepositions are also often referred to as fences and can extend from the edge regions or lateral regions of the sequence of layers also out of the plane of the substrate and, in particular, out of the plane of the topmost layer of the sequence of layers of the capacitor device.
In accordance with a particularly preferred embodiment of the method according to the invention, it is provided that the first intermediate layer is in each case filled essentially flush up to the level of the topmost layer of the capacitor device by a procedure in which, after the application of the intermediate layer, regions of the intermediate layer material which in each case project above the level of the topmost layer of the capacitor device are essentially eroded, in particular polished down, to the level of the topmost layer and of the capacitor device. This can be done in particular through the use of a CMP method, namely a chemical mechanical polishing method, or the like. The effect of the erosion to the level of the topmost layer of the capacitor device is that the surface of the topmost layer of the capacitor device is essentially not covered by the first intermediate layer.
What is achieved by the measure described last is that the redepositions or fences projecting above the level of the topmost layer are initially concomitantly embedded in the material of the intermediate layer that is first to be applied and are thus stabilized against breaking. The subsequent erosion of the material of the first intermediate layer down to the level of the topmost layer of the capacitor device, in particular through the polishing in the CMP method, is achieved such that the redepositions or fences are also removed down to the level of the topmost layer of the capacitor device. This makes it possible to effectively prevent particularly the risk of an electrical contact or short circuit between the layers of the capacitor device.
Although it suffices, in principle, after the application of the first intermediate layer and, if appropriate, the erosion or polishing-down thereof to the level of the topmost layer of the capacitor device, to directly form a corresponding metalization layer on the first intermediate layer for the purpose of contact-connecting the capacitor device, it is particularly advantageous, however, if, in accordance with a further preferred mode of the method according to the invention, a second, in particular essentially electrically insulating, intermediate layer is applied to the first intermediate layer and/or the topmost layer of the capacitor device, in particular in order that an electrical contact, short circuits or the like in each case among layers of the capacitor device, for example on account of redepositions, fences or the likexe2x80x94precisely in the edge region or lateral region of the sequence of layersxe2x80x94are reduced or avoided to the greatest possible extent during operation.
After the application of the second intermediate layer, if appropriate the corresponding contact layer is then applied to and/or patterned onto the second intermediate layer, in which casexe2x80x94as has already been described abovexe2x80x94the contact layer is contact-connected to the topmost layer of the capacitor device in a central region and/or in a region remote from the edge thereof. What is achieved by these measures is that regions of the redepositions or fences which extend as far as the level of the topmost layer of the capacitor device and, if appropriate, terminate with this are covered by the second intermediate layer, which is likewise formed such that it is electrically insulating, and this then has the result of preventing electrical contact of the redepositions of the layers, which lie one above the other, directly among one another or indirectly via the contact layer and thus prevents electrical contact between these layers.
In a further preferred mode of the method according to the invention it is provided that essentially the same material, in particular a dielectric such as SiOx or the like, is used for the first and for the second intermediate layer. To supplement this or as an alternative to this, it is provided that both intermediate layers are applied in a common process step, as a result of which particularly a simple method control is produced and presupposes, however, that the redepositions or fences which extend beyond the level of the topmost layer of the capacitor device have been removed in another way beforehand or else are not present in this form.
During the application and patterning of the layers for the capacitor devices, it is also important in the single-step method to avoid possible chemical conversion processes, in particular oxidations or the like, of the individual layers with the process atmosphere.
In accordance with a further mode of the invention, it is provided that the sequence of layers for the at least one capacitor device is constructed through the use of a 2D patterning method on the substrate.
This is done, in particular, by the layers in each case being applied in a whole-area and/or large-area manner, preferably in a common process step, on the substrate and then subsequently being patterned in an etching operation or the like, preferably in a common process step and, if appropriate, after a heat treatment step, e.g. an O2 annealing step, at relatively high temperatures. The large-area configuration of the layers means that the attack area at the lateral areas or lateral edge regions of the layer structure is kept particularly small, so that chemical conversion processes or oxidations precisely cannot occur in particular in those regions which are then reconstructed by the method step of patterning to form the actual layer sequences of the capacitor devices.
Therefore, it is preferred that, during the etching operation or the like, essentially a plasma process or the like, preferably in an argon- and/or chlorine-containing atmosphere, is carried out, preferably using resist mask configurations or the like. By virtue of this procedure, a particularly favorable imaging behavior can be achieved through the setting of the argon/chlorine mixture and the use of resist masks during the plasma process or sputtering process, so that faceting effects and dimensional expansions are avoided to the greatest possible extent.
It is furthermore preferred that, in the sequence of layers of the capacitor device, in each case at least a lower electrode layer, an upper electrode layer and, in between, a dielectric layer are formed, the lower electrode layer being made such that it essentially faces the substrate and the upper electrode layer being made such that it is essentially remote from the substrate. As a result, a capacitor device in the form of a layer structure is formed in a particularly suitable manner, the lower electrode layer serving as a bottom electrode and the upper electrode layer serving as a top electrode.
In order to ensure that the structures formed below the capacitor device in the substrate are protected during fabrication and during operation, in accordance with a further mode of the invention it is provided that a barrier layer is formed between the substrate and the lower electrode layer or bottom electrode, in particular in order that surface regions of the substrate are shielded and protected from a process gas, in particular from oxygen or the like, during patterning, during further processing steps and/or during operation.
In particular, ferroelectric and/or paraelectric materials are used as dielectric material. SrBi2(Ta,Nb)2O9 (SBT, SBTN), Pb(Zr,Ti)O3 (PZT)), Bi4Ti3O12 (BTO), (Ba,Sr)TiO3 (BST) or the like are particularly suitable in this case.
In particular, an oxygen-resistant, metallic material, in particular a noble metal or the like, is suitable as materials for the lower and/or the upper electrode layer. Pt, Pd, Ir, Rh, Ru, RuOx, IrOx, RhOx, SrRuO3, LSCO (LaSrCoOx), YBa2Cu3O7, high-temperature super-conductors or the like are preferred in this case.
Essentially a dielectric material, e.g. silicon oxide or the like, is provided as a material for the at least one intermediate layer.
Platinum, aluminum and/or the like is particularly suitable as material for the contact layer.
Preferably, the corresponding capacitor devices and their layer structures are in each case applied in the region of a plug of the substrate or the like.
During the patterning of the capacitor device or capacitor devices, in particular in the context of a 2D patterning operation, it is possible to use, in principle, so-called resist masks or the like at moderate etching temperatures. However, a particularly advantageous mode of the method according to the invention uses, for the patterning of the capacitor device, in each case a hard mask, in particular made of silicon oxide or the like, preferably in the context of a hot cathode etching operation. This procedure has the advantage that at most slight redepositions or fences occur during the etching process itself. Resist masks are not suitable, however, for such a high-temperature etching process.
After the actual patterning operation, namely the etching, part of the hard mask has been eroded by the etching operation itself, but part of the hard masks is still situated on the topmost layer of the capacitor devices, namely e.g. the top electrode. This covering layer on the top electrode in the form of the hard-mask residue can be eroded e.g. by a corresponding polishing methodxe2x80x94e.g. a CMP methodxe2x80x94down to the level of the surface of the top electrode. It is advantageous in this case for the intermediate regions between the patterned capacitor devices and, consequently, the semiconductor substrate surfaces that have remained free to be filled beforehand with at least one intermediate layer. What is achieved as a result is that the patterned capacitor devices are mechanically stabilized during the actual polishing method.
In this case, the hard-mask residue is preferably also concomitantly embedded in the intermediate layer, e.g. by correspondingly selecting the layer thickness of the intermediate layer correspondingly beyond the level of the surface of the top electrode.
In accordance with this mode of the invention, then, after the patterning of the capacitor device, the latter and the hard mask on the top electrode are embedded in at least one common intermediate layer and then subsequently polished down to the level of the surface of the top electrode.
Further properties and aspects of the invention can be summarized as explained below:
In order to fabricate ferroelectric capacitors for applications in nonvolatile semiconductor memories having a high integration density, a ferroelectric material, for example SrBi2(Ta,Nb)2O9 (SBT, SBTN), Pb(Zr,Ti)O3 (PZT), Bi4Ti3O12 (BTO), (Ba,Sr)TiO3 (BST) or the like, is used as a dielectric between the electrodes of a capacitor. Paraelectric materials, such as, for example, (Ba,Sr)TiO3 (BST), can also be used. The electrode material is a noble metal which withstands high temperatures in oxygen. Appropriate materials for this are Pt, Pd, Ir, Rh, Ru, RuOx, IrOx, RhOx, SrRuO3, LSCO (LaSrCoOx), YBa2Cu3O7 and high-temperature superconductors. In general, the capacitor construction involves, in a conventional manner, either following the technologically more demanding stacked principle or else proceeding according to the offset cell principle, which takes up a great deal more space.
A high integration density is generally achieved only using a so-called single-step method, because the latter allows steep sidewalls on the patterned layer structures since appreciable dimensional expansions and faceting of the masks do not occur.
Both the stacked principle and the offset principle require process steps for patterning the electrodes of the capacitor devices, namely the lower electrode or bottom electrode and the upper electrode or top electrode. During the patterning of new electrode materials such as platinum, for example, a plasma process or sputtering process is typically used in the case of large scale integration. The material erosion from the coated substrate in the unmasked regions on the substrate wafer is effected by the sputtering removal under bombardment e.g. with chlorine ions and/or argon ions.
In order to be able to realize very small and fine structures dimensionally accurately, it is necessary that the structure of the resist mask can be transferred to the platinum layer or the like which is to be patterned, without changing the so-called critical dimension (CD). However, primarily when reactive process gases are used, a sputtering attack of ions leads to faceting, beveling or tapering of the resist mask and, consequently, to corresponding faceting when transferring the structure, for example in platinum. This faceting limits the size of the smallest structures that can be obtained.
It is known that the most severe faceting is established in pure chlorine plasmas. By contrast, with an increasing proportion of argon in a chlorine/argon mixture, the sidewall angle increases during the material erosion. On the other hand, the use of pure noble gas as process gas during the plasma etching admittedly results in practically no faceting of the resist mask and, accordingly, no faceting or beveling of the transferred structure. As a consequence, however, so-called redepositions or fences can form at the etching edge obtained, that is to say e.g. in the lateral region or edge region of the layer structure to be applied. The redepositions or fences are particularly high if the layer structure of the capacitor device to be applied, namely the sequence of barrier layer or oxygen barrier, bottom electrode, ferroelectric dielectric and top electrode, is formed in one step.
As has already been explained above, the invention""s process of filling with an intermediate layer or with an intermediate oxide beyond the level of the topmost layer of the capacitor devices, redepositions or fences which project beyond the level of the topmost layer of the capacitor device being embedded precisely in the intermediate oxide, and the subsequent process of polishing back down to the level of the topmost layer of the capacitor device are advantageous because the fences or redepositions, which can lead to short circuits between the layers of the sequence of layers of the capacitor device, are prevented to the greatest possible extent by these measures. Short circuits could happen to subsequent levels of metallization, or, after breaking or bonding of fences, to neighboring structures.
A further problem is the oxidation of structures in the region of the surface or below the surface of the substrate during further process steps that are to be completed after the application of the layers. In this case, it is particularly problematic that in a plurality of ferroelectric dielectrics during the formation of a complete ceramic structure and during annealing, oxygen is absolutely necessary as the process atmosphere.
In order in this case to prevent oxidation, in particular of polysilicon plugs or of W plugs, an essentially electrically conductive oxygen barrier or barrier layer is required as the bottommost layer, that is to say as the layer between the bottommost electrode layer and the substrate surface. It is known that during the patterning in stages of the capacitor device or of the layer sequence of the capacitor device, that is to say during separate patterning of barrier layer, bottom electrode, ferroelectric and top electrode, during conventional patterning methods and fabrication methods of capacitor devices, the contact layers in the barrier stack can be oxidized from the side, that is to say from lateral regions or edge regions, during oxygen annealing, and that in this case the bottom electrode connection toward the substrate, in particular toward the corresponding plugs, can be at least partially destroyed.
The barrier layer may also have a layer sequence, e.g. TaSi/TaSiN or the like.
By contrast, in the case of the above-described mode of the method according to the invention for fabricating the capacitor devices of a capacitor configuration, the large-area or whole-area formation of the layer structure for the respective capacitor devices on the entire wafer, i.e. on the entire substrate, means that a particularly large overlap between the individual layers is produced and, as a result, degradation of the oxygen barriers and of the plug structures in the substrate is prevented. Specifically, it has been shown that the overlap between bottom electrode/lower electrode layer and underlying barrier layer is of particular importance. The larger this overlap between the layers is made, the fewer oxidation processes can act from the side on the oxygen barrier and thus on the contact between plug and bottom electrode. Consequently, this means that more capacitors are produced, according to the invention, in the capacitor configuration with a higher quality and/or yield. In this case, it is of particular importance that all the coating processes, heat treatments and annealing processes which are required for fabricating the ferro-electric capacitor or the like are initially carried out on the whole-area layers. Only afterward is the configuration of the individual capacitors on the substrate realized in a single etching step or in a plurality of etching steps, in which case, after the embedding process in the intermediate oxide, the redepositions or fences then subsequently have to be polished down.
This means, then, that after the patterning of the individual capacitor modules, in one step in each case, an embedding process for example in silicon oxide as an intermediate oxide is performed, the projecting intermediate oxide then subsequently being polished, for example through the use of a CMP method, down to the level of the top electrodes, with the result that the top electrodes are uncovered and ready for further coating, either with a further intermediate oxide or dielectric or directly with a contact layer.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a capacitor configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.